Multiplication by 0,6

Please note that there's no need to perform the actual /32 division. You can simply multiply 19 and discard the 5 LSB.

Moreover multiplication *19 can be reduced to a three terms addition:

CAM_DATA*16 + CAM_DATA*2 + CAM_DATA*1

which is equivalent to:

result <= ("0" & CAM_DATA & "0000") + ("0000" & CAM_DATA & "0") + ("00000" & CAM_DATA)

where result is std_logic_vector(12 downto 0).

Then:

array_amp_to_find(column_counter) <= result(12 downto 5);

So, neither an actual multiplier is required.

I think this can be easily synthesized to work in a single cycle.

(I'm not sure about this VHDL syntax, please check; I'm used with Verilog)

Regards