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Honored Contributor

14 years ago

multiple read pointers on SDRAM

I'm using the DE2 board and can successfully write and read back audio samples from the SDRAM. I can now control the location of the read pointer for delays etc- basic stuff for you lot but pretty fu...

Altera_Forum

Honored Contributor

14 years ago

As Daixiwen explained, the SDRAM accesses have to be sequential by nature. The SOPC interface adds some overhead to it, so for maximum throughput respectively number of taps, a pure HDL design would be reasonabble. I'm however under the impression, that a SOPC based access will allow many taps for usual audio sampling rates, e.g. 44 kHz.

You can write a simple test program to determine the available interface speed.

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multiple read pointers on SDRAM

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