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Altera_Forum
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16 years ago

Multiple instances of VHDL file on one device

Hi everyone I've managed to generate a FIFO using the megafunctions in Quartus. I was wandering if there is an easy way of putting two of these FIFOs onto one device without lots of extra VHDL ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thank you for the quick response.

I've done what you recommended and I've now got two instances of the fifo in a schematic but if I try to run analysis and synthesis it tells me that "the top partition does not contain any logic"

I haven't put any wires in because i want the outputs of both fifos to appear on the pins of the FPGA. Are there any more pointers you can give me?

Thanks again

Dan