Honored ContributorHi everyone
I've managed to generate a FIFO using the megafunctions in Quartus. I was wandering if there is an easy way of putting two of these FIFOs onto one device without lots of extra VHDL programming. My skills in VHDL are not that substantial! The reason is that I need a to channel (input and output) buffer. Any help greatly appreciated Dan
Honored Contributorif you really want to avoid VHDL you can make sure the .bsf box is checked in the MegaWizard and insert multiple instances of the FIFO in a .bdf schematic file and wire them up.
or else search around for VHDL instantiation. its not all that difficult.Honored ContributorThank you for the quick response.
I've done what you recommended and I've now got two instances of the fifo in a schematic but if I try to run analysis and synthesis it tells me that "the top partition does not contain any logic" I haven't put any wires in because i want the outputs of both fifos to appear on the pins of the FPGA. Are there any more pointers you can give me? Thanks again DanHonored ContributorHonored ContributorAhh, I see, thanks again
DanHonored Contributorokay so now I have a schematic with the pins that i need my device to have wired into two instances of the FIFO, but when I run analysis & synthesis with that schematic as the top-level entity it says that the pins aren't driving any logic and when you run the fitter it says no logic elements are used..... I'm a little confused...
Honored Contributorcan you post a screen shot?
Honored ContributorHere is a couple of screenshots:-
The first one shows the pins being rejected and the second my top level schematic. I realize that now its at the point where its saying can't use type input, output or bidirectional pins, but that still equally confuses me :S thanks in advance DanHonored ContributorSimply connect all required FIFO control inputs.
