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Altera_Forum
Honored Contributor
Honored ContributorMultiple instances of VHDL file on one device
Hi everyone I've managed to generate a FIFO using the megafunctions in Quartus. I was wandering if there is an easy way of putting two of these FIFOs onto one device without lots of extra VHDL ...
Altera_ForumHonored Contributor
Honored Contributorokay so now I have a schematic with the pins that i need my device to have wired into two instances of the FIFO, but when I run analysis & synthesis with that schematic as the top-level entity it says that the pins aren't driving any logic and when you run the fitter it says no logic elements are used..... I'm a little confused...
