multiplayer in modelsim

It's only the first of many VHDL syntax errors. You should write

entity test is
end;

But you still need to declare signals in the architecture before assigning values to it. And a testbench is useless without driving a design under test.

If you don't like to read a text book or tutorial before writing code, you can still debug your attempts line by line. Review the first error line, compare with VHDL language reference, correct, compile again. Repeat until compiled with no errors. Then try to simulate.

There are by the way code tags (# button under go advanced) to format your code appropriately and make it better readable. And the question should be surely posted in the Coding/VHDL rather than General Altera Discussion section.