thanks but i wrote test bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test is MultTop
end;
architecture btest of test is
begin
Clk <= not Clk after 10 ns; -- 20ns period clock
process
begin
for i in 15 downto 0 loop -- 16 multiplier values
Multiplier <= std_logic_vector(to_unsigned(i,4));
for j in 15 downto 0 loop -- 16 multiplicand values
Multiplicand <= std_logic_vector(to_unsigned(j,4));
Start <= '0', '1' after 5 ns, '0' after 40 ns; -- 40 ns Start pulse
wait for 50 ns;
wait until Done = '1'; --Wait for completion of algorithm
assert (to_integer(UNSIGNED(Product)) = (i * j)) ? Check Product
report "Incorrect product" severity NOTE;
wait for 50 ns;
end loop;
end loop;
end process;
end btest;
but give this error:
near "MultTop": (vcom-1576) expecting END.