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Altera_Forum's avatar
Altera_Forum
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11 years ago

mSGDMA ST->MM fills FIFO immediately

Hi,

I would like to use mSGDMA in my application but it behaves differently from what I would expect. Currently, I have a Avalon ST source module connected to mSGDMA write master, controlled by mSGDMA dispatcher. Streaming source is my custom module which, if sink is ready, writes one word every few cycles. It bugs me that as soon as mSGDMA write master is brought out of reset, it fills its internal FIFO and waits for dispatcher to emit a command to write it on MM master port (see the attached image). I would prefer that Streaming transaction starts after I write a descriptor, so it would store most recent data.

Is there a setting for this I am missing out? The easiest solution I came up is writing two same descriptors consecutively, the first one will empty the FIFO and the second will overwrite MM data with fresh one. Is there maybe a more elegant solution?

However, I would still like to thank BadOmen for this fantastic module.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi janco,

    Did you figure this out? My FIFO isnt filling up immediately but it seems that once it does it doesnt get emptied and I start getting missed words from my avalon stream in my memory.

    It could be very helpful if you figured out why your FIFO wasnt being emptied.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    I think you misunderstood me, FIFO in my case gets emptied, but only after I write descriptors (that is a desired behaviour, since DMA should at least know where to write data to). My problem was that FIFO got filled up immediately. I resolved (covered up :)) this problem at driver level, by not reading that part of memory.