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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Modifying the PCIe DMA transfer example design for Arria 10 device.

Hello,

I have a modified version of the PCIe DMA transfer example design (mentioned in the Chapter 7 of attached user manual). As a modification to the example design, I added a custom generated data generator IP and an Avalon FIFO Memory Intel IP to the existing DMA transfer example design {Platform designer screenshot is attached as DMA_modified_part1.PNG and DMA_modified_part2.PNG} . My aim is to continuously generate data (bit stream) in the FPGA using a data generator custom IP (generated from the user Verilog code) and pass it through a FIFO to the DDR4 memory, and then do a DMA transfer though the PCIe to the host computer.

Basically, a continuous DMA read (just read) from the data saved in the FPGA DDR4 memory. After compilation without any error and programming into the FPGA, I am not able to read data using the modified API code(modification I meant, disabling the DMA write API in the API code) on the host computer from the DDR4 memory. As I am trying to debug, I appreciate your comments regarding the configurations I used, and I have the following questions:

1. I would like to make sure that the signals and interfaces that I have used to connect the Avalon FIFO Memory Intel IP to the PCIe DMA example design is correct (please see the attached screenshots). This IP have an input type of Avalon Streaming Sink and Output type of Avalon Memory Map Read. Do you have any comment regarding this selection of the configuration I used?

2. My data generator custom IP is designed to generate bit stream at a rate and runs with the same clock and reset as PCIe DMA Intel IP (In Platform Designer it’s named as DUT). Also, the custom IP have two exported inputs that connects to the two switches of the FPGA (to start and end to data generation respectively). To connect with the Avalon Streaming Sink of the Avalon FIFO Memory Intel IP, the custom data generator IP has an Avalon Streaming Source. Do you have any comments on sharing the reset signal from DUT with the data generator custom IP?

I am working in Arria 10 GX device (10AX115N2F45E1SG) and my host computer is based on windows 10. And I am using Quartus Prime Pro 18.4 version.

Thank you.

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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Sijith,


    I am not received the email that you have sent. Can you send it through Private Message then?

    I will ping you there.


    1) But from your reply I assume that even if nothing changed in DE5A_NET.v, the included ep_g3x8_avmm256 module maps the ep_g3x8_avmm256.v and so whatever changes ep_g3x8_avmm256.v have reflected in DE5A_NET.v?

    • Yes the top level design should call all module within it.


    2) If I create an EMIF example design and include the rtl code for counter part, how I can view from my host system that the data is getting written there? Is there any provision in the EMIF example design? Could you elaborate it bit more?

    • To view the data, you can use Signal Tap tool and monitor the signals from example design.
    • There is a Traffic Generator module that act as user logic controller.
      • You can monitor the signals from this module to check on read data after the read transaction has been performed.


    3) Do you have any suggestion regarding how to make a custom IP out-of counter.v code that is compatible for both synthesis and simulation?

    • I think it's better to have another thread for checking on this issue. Then the expertise will come to help on this issue.


    Regards,

    Adzim


  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi Adzim,

    It would be great if you ping me with the private email to send files. But for now, I would like to attach here the compressed folder contains my working directory regarding the integration of custom IP and FIFO with the DMA transfer example design. (it have counter.v in the directory and top-level DE5A_NET.v and all related files. just removedep_g3x8_avmm256_integrated_tb folder to reduce size.)

    1) I assume that since ep_g3x8_avmm256 module have instantiations of FIFO IP and Counter, we don't need them to instantiate in the top-level module DE5A_NET.v, right?

    2) Would be great if you could have a look in the g3x8_avmm256_integrated.qsys file in the platform designer system to see interface connections I used. Also great if you could have a look into my counter.v too.

    3) I am curious that if our counter IP (through FIFO IP) could write to DDR4 in EMIF example design, then the counter IP should be able to write in the DDR4 of the PCIe DMA transfer example design? {Is there any chance for the components in the PCIe DMA transfer example design which the EMIF example design example does not have will have any effect in the data transfer to DDR4} or your suggestion is just to check if the counter IP is capable of streaming data?

    Thank you.

  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi Adzim,

    1) As you suggested in our last meeting, I was trying to map the memory map slave address to the Base Address (the address value specified in the PCIe DMA example design API Code. To access the DDR4 A, the starting address specified in API was 0x20000000 with a size of 4GB (I assume, it means the address span is from 0x20000000 to 0x30000000?) , and for DDR4 B the address specified was 0x40000000 with 4GB size). But unfortunately, I could not succeeded in it as I was bit unclear about the place to put the address in the code. It would be great if you could help me in that. Also, I would like to make sure the code where we should do changes is in the PCIe_DDR4/ip/ep_g3x8_avmm526_integrated_fifo_9 folder (As shown in attachment Fifo_slaveaddress1.PNG)?

    2) I am wondering that is it possible to set the slave address parameter in the Platform Designer System (In the address space shown in attachments Addressmaps.PNG or Addressmap1.PNG) . If we can do it, when I was trying it I faced a difficulty: - {When I tried to change the adress maping of Avalon Memory map Slave address of "avalon fifo" component in Platform Designer (Addressmap1.PNG), I could change the address in the "Base" colum, but the corresponding "end" colum entry cannot change. Did I miss something that disable me to change it? (I was looking for a option in parameter editor in the Avalon FIFO IP, but could not see an option for it) }.

    3) I have a additional question for you, parallel to this I was just trying to simulate my counter Custom IP + Avalon FIFO IP to see the correct data wave form is getting out of this design (I could get a waveform out of counter.v code in the modelsim simulator). But I am confused how I can simulate it when have I have them in the Platform Designer as IP's. I remember you mentioned me you did simulate the counter+EMIF Example design. It would be great you could mention how to do it (or any link that can help?). I could not find any RTL simulation tool in my Quartus Prime Pro. What I was trying to do is, a) After generating HDL and generating testbench, b) Executed `Generate simulation for IP`, I assume it generates simulation files in the project directory?. c) Then I tried to open a new IntelFPGA modelsim project and added all verilog codes (corresponding to all components) from the ip/<component_name>/synth folder of my project to it and try to run it. But I assume this is not what we are suppose to do?

    Thank you very much and please let me know if you have any question.