Modifying the PCIe DMA transfer example design for Arria 10 device.

Hi Adzim,

It would be great if you ping me with the private email to send files. But for now, I would like to attach here the compressed folder contains my working directory regarding the integration of custom IP and FIFO with the DMA transfer example design. (it have counter.v in the directory and top-level DE5A_NET.v and all related files. just removedep_g3x8_avmm256_integrated_tb folder to reduce size.)

1) I assume that since ep_g3x8_avmm256 module have instantiations of FIFO IP and Counter, we don't need them to instantiate in the top-level module DE5A_NET.v, right?

2) Would be great if you could have a look in the g3x8_avmm256_integrated.qsys file in the platform designer system to see interface connections I used. Also great if you could have a look into my counter.v too.

3) I am curious that if our counter IP (through FIFO IP) could write to DDR4 in EMIF example design, then the counter IP should be able to write in the DDR4 of the PCIe DMA transfer example design? {Is there any chance for the components in the PCIe DMA transfer example design which the EMIF example design example does not have will have any effect in the data transfer to DDR4} or your suggestion is just to check if the counter IP is capable of streaming data?

Thank you.