Modifying the PCIe DMA transfer example design for Arria 10 device.

Hi Adzim,

1) As you suggested in our last meeting, I was trying to map the memory map slave address to the Base Address (the address value specified in the PCIe DMA example design API Code. To access the DDR4 A, the starting address specified in API was 0x20000000 with a size of 4GB (I assume, it means the address span is from 0x20000000 to 0x30000000?) , and for DDR4 B the address specified was 0x40000000 with 4GB size). But unfortunately, I could not succeeded in it as I was bit unclear about the place to put the address in the code. It would be great if you could help me in that. Also, I would like to make sure the code where we should do changes is in the PCIe_DDR4/ip/ep_g3x8_avmm526_integrated_fifo_9 folder (As shown in attachment Fifo_slaveaddress1.PNG)?

2) I am wondering that is it possible to set the slave address parameter in the Platform Designer System (In the address space shown in attachments Addressmaps.PNG or Addressmap1.PNG) . If we can do it, when I was trying it I faced a difficulty: - {When I tried to change the adress maping of Avalon Memory map Slave address of "avalon fifo" component in Platform Designer (Addressmap1.PNG), I could change the address in the "Base" colum, but the corresponding "end" colum entry cannot change. Did I miss something that disable me to change it? (I was looking for a option in parameter editor in the Avalon FIFO IP, but could not see an option for it) }.

3) I have a additional question for you, parallel to this I was just trying to simulate my counter Custom IP + Avalon FIFO IP to see the correct data wave form is getting out of this design (I could get a waveform out of counter.v code in the modelsim simulator). But I am confused how I can simulate it when have I have them in the Platform Designer as IP's. I remember you mentioned me you did simulate the counter+EMIF Example design. It would be great you could mention how to do it (or any link that can help?). I could not find any RTL simulation tool in my Quartus Prime Pro. What I was trying to do is, a) After generating HDL and generating testbench, b) Executed `Generate simulation for IP`, I assume it generates simulation files in the project directory?. c) Then I tried to open a new IntelFPGA modelsim project and added all verilog codes (corresponding to all components) from the ip/<component_name>/synth folder of my project to it and try to run it. But I assume this is not what we are suppose to do?

Thank you very much and please let me know if you have any question.