Forum Discussion
AdzimZM_Altera
Regular Contributor
2 years agoHi Sijith,
I am not received the email that you have sent. Can you send it through Private Message then?
I will ping you there.
1) But from your reply I assume that even if nothing changed in DE5A_NET.v, the included ep_g3x8_avmm256 module maps the ep_g3x8_avmm256.v and so whatever changes ep_g3x8_avmm256.v have reflected in DE5A_NET.v?
- Yes the top level design should call all module within it.
2) If I create an EMIF example design and include the rtl code for counter part, how I can view from my host system that the data is getting written there? Is there any provision in the EMIF example design? Could you elaborate it bit more?
- To view the data, you can use Signal Tap tool and monitor the signals from example design.
- There is a Traffic Generator module that act as user logic controller.
- You can monitor the signals from this module to check on read data after the read transaction has been performed.
3) Do you have any suggestion regarding how to make a custom IP out-of counter.v code that is compatible for both synthesis and simulation?
- I think it's better to have another thread for checking on this issue. Then the expertise will come to help on this issue.
Regards,
Adzim