modelsim vsim-3601 on counter

Couldn't the problem come from the testbench? I don't see anything wrong in your code...

This behaviour happens with the tesbench (which just sets the clock and hits the reset at the beginning) and simply through forcing the clock/reset directly.

I saved your code in a file counter.vhd, adding the correct library calls. I then created this test bench, saved as countertb.vhd:

library ieee;
use ieee.std_logic_1164.all;
entity TestBench is
end entity;
architecture bench of TestBench is
	component bcdcounter
	port (
		clk : in std_logic;
		reset : in std_logic;
		count : out std_logic_vector(3 downto 0);
		fullcount : out std_logic
	);
	end component;
	
	signal clk		: std_logic;
	signal reset	: std_logic;
	signal count	: std_logic_vector(3 downto 0);
	signal fullcount : std_logic;
	
	signal stoptest : std_logic;
begin
	UUT : bcdcounter port map (clk,reset,count,fullcount);
	
	ClkGen : process
	begin
		while stoptest /= '1' loop
			clk <= '1';
			wait for 5 ns;
			clk <= '0';
			wait for 5 ns;
		end loop;
		wait;
	end process;
	
	SigGen : process
	begin
		reset <= '1';
		wait for 25 ns;
		reset <= '0';
		wait until fullcount = '1';
		wait for 100 ns;
		stoptest <= '1';
		wait;
	end process;
	
end architecture;

vlib lib
vmap work lib
vcom -O0 counter.vhd
vcom -O0 countertb.vhd
vsim -novopt TestBench
add wave /* 
run -all
wave zoomfull

wangahrah - you're right look through your loops in your testbench. This sort of thing usually happens when you get a self referencing loop with no time delay in it.

Update-