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Honored Contributormodelsim vsim-3601 on counter
Hi folks-
The following code returns in modelsim a # ** Error: (vsim-3601) Iteration limit reached at time 0 ps. when I run the simulation. However, when I step through the program, I see the counter working as intended. I know 3601 often comes when there's trouble in a loop, but I'm having trouble locking down where the problem is, and confused as to why the simulation runs when single-stepped through, but otherwise fails. Any thoughts would be very helpful. Thanks! Michael entity bcdcounter is port ( clk : in std_logic; reset : in std_logic; count : out std_logic_vector(3 downto 0); fullcount : out std_logic ); end bcdcounter; architecture rtl of bcdcounter is signal count_s : std_logic_vector(3 downto 0); begin count <= count_s; bcdcount: process(clk,reset) begin if reset='1' then count_s <= "0000"; fullcount <= '0'; elsif (rising_edge(clk)) then if count_s = "1001" then count_s <= "0000"; fullcount <='1'; else count_s <= count_s +"1"; fullcount <='0'; end if; end if; end process; end rtl;5 Replies
Altera_ForumUpdate-
I've checked with some other folks at my location...everything runs fine for them. This appears to be a problem with my Altera Modelsim. All the simulations run fine for other people, running the same version, etc etc. I've tried reinstalling the Quartus suite + modelsim, but still run into the same problems, using their ini files and settings. If anyone has any other ideas, let me know. Otherwise, many thanks for your help and looking over the code for me. Michael- Altera_Forum
wangahrah - you're right look through your loops in your testbench. This sort of thing usually happens when you get a self referencing loop with no time delay in it.
Taking Daixiwen's testbench, another way of writing the first process would be: clk <= not clk after 5 ns when stoptest /= '1'; (provided clk has an initial value in its declaration). if you mistyped it e.g.: clk <= not clk when stoptest /= '1'; then the concurrent statement would keep getting called to invert the clk without ever advancing simulation time (and you'd probably get the same error message that you got). - Altera_Forum
I saved your code in a file counter.vhd, adding the correct library calls. I then created this test bench, saved as countertb.vhd:
And used this compile script in Modelsim:library ieee; use ieee.std_logic_1164.all; entity TestBench is end entity; architecture bench of TestBench is component bcdcounter port ( clk : in std_logic; reset : in std_logic; count : out std_logic_vector(3 downto 0); fullcount : out std_logic ); end component; signal clk : std_logic; signal reset : std_logic; signal count : std_logic_vector(3 downto 0); signal fullcount : std_logic; signal stoptest : std_logic; begin UUT : bcdcounter port map (clk,reset,count,fullcount); ClkGen : process begin while stoptest /= '1' loop clk <= '1'; wait for 5 ns; clk <= '0'; wait for 5 ns; end loop; wait; end process; SigGen : process begin reset <= '1'; wait for 25 ns; reset <= '0'; wait until fullcount = '1'; wait for 100 ns; stoptest <= '1'; wait; end process; end architecture;
And it runs fine. So the problem doesn't come from your code.vlib lib vmap work lib vcom -O0 counter.vhd vcom -O0 countertb.vhd vsim -novopt TestBench add wave /* run -all wave zoomfull - Altera_Forum
This behaviour happens with the tesbench (which just sets the clock and hits the reset at the beginning) and simply through forcing the clock/reset directly.
However, perhaps this piece of the puzzle will mean something...when I single step, I do not get this error, and the counter increments, pulses the fullcount, and resets itself fine. Doesn't get stuck in any loop. But running it for any time results in the iteration error. At some (seemingly random) point, the wave stops drawing, but I still see the signals incrementing as they should. Thanks for your thoughts/help, Michael - Altera_Forum
Couldn't the problem come from the testbench? I don't see anything wrong in your code...
