modelsim vsim-3601 on counter

wangahrah - you're right look through your loops in your testbench. This sort of thing usually happens when you get a self referencing loop with no time delay in it.

Taking Daixiwen's testbench, another way of writing the first process would be:

clk <= not clk after 5 ns when stoptest /= '1';

(provided clk has an initial value in its declaration).

if you mistyped it e.g.:

clk <= not clk when stoptest /= '1';

then the concurrent statement would keep getting called to invert the clk without ever advancing simulation time (and you'd probably get the same error message that you got).