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Altera_Forum's avatar
Altera_Forum
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16 years ago

Modelsim: Unknown State

In the modelsim simulation, there is a signal, delay1, shows its value and undefined state(red colour) periodically. It shouldn't show unknown state based on my code. I wonder why. Pls have a look...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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I'm not a verilog expert, but it seems that you define q1 and q2 as tables with indexes between 1 and num_shiftreg, and set delay1 with q1[no_shiftreg] or q2[no_shiftreg].

But you also initialize no_shiftreg with the value 0. So in those cases delay1 will take an uninitialized value. You should either initialize no_shiftreg with 1 or use q1[no_shiftreg+1] / q2[no_shiftreg+1]

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Hi Daixiwen,

you are right. q1[0] and q2[0] are never intialized, but used as input for Delay1.

Kind regards

GPK