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Altera_Forum's avatar
Altera_Forum
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15 years ago

modelsim lpm devide error

Hi

I am trying to run a simulate in modelsim

And I got those errors:

# ** Error: C:/vhdl/modelsim/state maschine/Steer_Encoder.vhd(86): Actual (function call "conv_std_logic_vector") for formal "numer" is not a globally static expression.

# ** Error: C:/vhdl/modelsim/state maschine/Steer_Encoder.vhd(87): Actual (function call "conv_std_logic_vector") for formal "denom" is not a globally static expression.

# ** Error: C:/vhdl/modelsim/state maschine/Steer_Encoder.vhd(107): Actual (function call "conv_std_logic_vector") for formal "numer" is not a globally static expression.

# ** Error: C:/vhdl/modelsim/state maschine/Steer_Encoder.vhd(108): Actual (function call "conv_std_logic_vector") for formal "denom" is not a globally static expression.

I also found those possible solutions but didn't succeeded in implementing them

1. To change the case sensitive in the compiler

"To fix this problem, edit the wrapper file and change the LPM parameters to lower case before compiling"

2. To create a library for the lpm component being used

"

creating simulation libraries

Simulation libraries are required to simulate a design that contains an Altera

primitive, LPM function, or Altera megafunction. Depending on your design, you

must create the required simulation libraries and link them to your design correctly."

Tanks in advance

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It sounds like you're trying to call the conv_std_logic_vector function on a port map. You need a temporary signal to call the function then map the temporary signal to the lpm_divide port.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    thanks

    I added signals and made and called the conv function outside the component and that solved it.

    but now the compiler gives errors on the components with ports that connecting to signals in the fsm

    while some ports are external ports other are ports that connect between signals in the general code so the compiler won't recognize them.

    I can't leave them as open

    I can't ignore them

    and I can't insert them to themselves

    what should I do?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    
entity fsm_tb is   
end entity fsm_tb;
architecture arc_fsm_tb of fsm_tb is
--======================  fsm ports ===========================================         
   signal System_Clk_50MHz   :  std_logic:= '0'; -- 
   signal System_N_Reset   :  std_logic:= '0'; -- 
   signal FSM_enable_led    :  std_logic:= '0'; -- 
   signal FSM_init_led    :  std_logic:= '0'; -- 
   signal FSM_type_led    :  std_logic:= '0'; -- 
   signal FSM_stop_led    :  std_logic:= '0'; -- 
--======================  communication ports ===========================================         
   signal UART_baud_sel     :  std_logic_vector(2 downto 0):= (others => '0'); -- 
   signal UART_rx           :  std_logic:= '0'; -- 
   signal UART_tx           :  std_logic:= '0'; -- 
   signal led_sec        :  std_logic:= '0'; -- 
   signal UART_rxerr_led    :  std_logic:= '0'; -- 
   signal UART_txbusy       :  std_logic:= '0'; -- 
   signal UART_rx_done      :  std_logic:= '0'; -- 
   signal UART_dout         :  std_logic_vector(7 downto 0):= (others => '0'); -- 
   signal UART_ready_tx     :  std_logic:= '0'; -- 
     
 
--======================  motion encoder ports ===========================================         
   signal M_E_done    :  std_logic:= '0'; -- 
   signal M_E_DataIn    :  std_logic:= '0';-- 
      
--======================  steer encoder ports ===========================================         
   signal S_E_done    :  std_logic_vector (2 downto 0):= (others => '0'); -- 
   signal S_E_DataIn    :  std_logic_vector (1 downto 0):= (others => '0'); -- 
    
--======================  motion pwm ports ===========================================         
   signal M_P_Pwm     :  std_logic:= '0'; -- 
    
--======================  steer pwm ports ===========================================         
   signal S_P_Pwm     :  std_logic:= '0';-- 
   
component Steer_Pwm is
 generic (
    DC: time:=17 ms;    -- changeable
    clock_period: time:=20 ns;  -- changeable 
    max_pulse: time:= 1 ms;   -- changeable
    min_pulse: time:= 2 ms;   -- changeable
    neutral_pulse: time:= 1.5 ms -- changeable 
   );
 port (
    Rst : In  std_logic;      -- joined Rst to the FSM system 
    Clk : In  std_logic;      -- joined clock to the FSM system
    Enable : in std_logic;      -- Enable Steer motor
    Pwm : Out std_logic;       -- PWM pulse
    pulse_length : in integer
   );
end component Steer_Pwm;
component Motion_Pwm is
 generic (
    DC: time:=17 ms;    -- changeable
    clock_period: time:=20 ns;  -- changeable 
    max_pulse: time:= 1 ms;   -- changeable
    min_pulse: time:= 2 ms;   -- changeable
    neutral_pulse: time:= 1.5 ms -- changeable 
   );
 port (
    Rst : In  std_logic;
    Clk : In  std_logic;
    Enable : in std_logic;
    Pwm : Out std_logic;
    pulse_length : in integer
   );
end component Motion_Pwm;
component Steer_Encoder is
 port (
    done:   out std_logic_vector (2 downto 0);
    Rst:  in std_logic;
    Enable: in std_logic;
    Clk:  in std_logic;
    DataIn:  in std_logic_vector (1 downto 0);
    angle:  in integer;
    slot_number:  in integer;
    spare:  out integer;
    turns_number:  out integer;
    res:  in integer;
    spare_flag:  in std_logic;
    turn_flag:  in std_logic;
    turn_pulse: in integer
   );
end component Steer_Encoder;
component Motion_Encoder is
 port (
    done:   out std_logic;
    Rst:  in std_logic;
    Enable: in std_logic;
    Clk:  in std_logic;
    DataIn:  in std_logic;
    distance:  in integer;
    slot_number:  in integer;
    wheel_radius:  in integer
   );
end component Motion_Encoder;
component Communication is
 generic (  ndbits          : natural   := 8);
 port (
    Clk  : in  std_logic;
    Rst  : in  std_logic;
    baud_sel  : in  std_logic_vector(2 downto 0);
    rx        : in  std_logic;
    tx        : out std_logic;
    led_sec   : out std_logic;
    rxerr_led : out std_logic;
    txbusy    : out std_logic;
    rx_done   : out std_logic;
    dout      : out std_logic_vector(7 downto 0);
    ready_tx  : in std_logic;
    din  : in std_logic_vector(7 downto 0)
   );
end component Communication;
 
begin
  
  test : entity work.fsm
generic map (
   DC => 17 ms,
   clock_period => 20 ns,
   max_pulse => 1 ms,
   min_pulse => 2 ms,
   neutral_pulse => 1.5 ms
   )
port map (
--======================  fsm ports ===========================================         
    System_Clk_50MHz  => System_Clk_50MHz, 
    System_N_Reset  => System_N_Reset, 
    FSM_enable_led  => FSM_enable_led, 
    FSM_init_led  =>FSM_init_led, 
    FSM_type_led  => FSM_type_led, 
    FSM_distance_value_led  => FSM_distance_value_led, 
    FSM_stop_led  =>FSM_stop_led, 
    FSM_angle_value_led  => FSM_angle_value_led, 
--======================  communication ports ===========================================         
    UART_baud_sel  =>UART_baud_sel, 
    UART_rx  => UART_rx, 
    UART_tx  => UART_tx, 
    led_sec=> led_sec, 
    UART_rxerr_led  => UART_rxerr_led, 
    UART_txbusy    => UART_txbusy, 
    UART_rx_done=> UART_rx_done, 
    UART_dout=> UART_dout, 
    UART_ready_tx=> UART_ready_tx, 
     
 
--======================  motion encoder ports ===========================================         
    M_E_done=> M_E_done, 
    M_E_DataIn=> M_E_DataIn, 
      
--======================  steer encoder ports ===========================================         
    S_E_done => S_E_done, 
    S_E_DataIn => S_E_DataIn,
    
--======================  motion pwm ports ===========================================         
    M_P_Pwm=> M_P_Pwm, 
    
--======================  steer pwm ports ===========================================         
    S_P_Pwm => S_P_Pwm
   
   );
  
steer_pwm_comp: Steer_Pwm generic map ( 
           DC => 17 ms,
           clock_period => 20 ms,
           max_pulse => 1 ms,
           min_pulse => 2 ms,
           neutral_pulse => 1.5 ms
          )
       port map (
           Rst => System_N_Reset,
           Clk => System_Clk_50MHz,
           Enable => S_P_En,
           Pwm => S_P_Pwm,
           pulse_length => S_FSM_S_P_pulse_length
          );
          
motion_pwm_comp:Motion_Pwm generic map ( 
           DC => 17 ms,
           clock_period => 20 ms,
           max_pulse => 1 ms,
           min_pulse => 2 ms,
           neutral_pulse => 1.5 ms
          )
       port map (
           Rst => System_N_Reset,
           Clk => System_Clk_50MHz,
           Enable => M_P_En,
           Pwm => M_P_Pwm,
           pulse_length => S_FSM_M_P_pulse_length
          );
Uart_comp:communication  generic map (  
           ndbits  => 8
          )
       port map (
           Clk => System_Clk_50MHz,
           Rst  => System_N_Reset,
           baud_sel => UART_baud_sel,
           rx => UART_rx,
           tx => UART_tx,
           led_sec => led_sec,
           rxerr_led => UART_rxerr_led,
           txbusy => UART_txbusy,
           rx_done => UART_rx_done,
           dout => UART_dout,
           ready_tx => UART_ready_tx,
           din => S_FSM_dout_reg
          );
M_Encoder_comp:Motion_Encoder 
       port map (
           done => S_M_E_done,
           Rst => System_N_Reset,
           Enable => M_E_En,
           Clk => System_Clk_50MHz,
           DataIn => M_E_DataIn,
           distance => S_FSM_distance,
           slot_number => S_FSM_slot_number,
           wheel_radius => S_FSM_Wheel_radius
          );
S_Encoder_comp:Steer_Encoder 
       port map (
           done => S_S_E_done,
           Rst => System_N_Reset,
           Enable => S_E_En,
           Clk => System_Clk_50MHz,
           DataIn => S_E_DataIn,
           angle => S_FSM_angle,
           slot_number => S_FSM_slot_number,
           spare => S_FSM_spare_angle,
           turns_number => S_FSM_turns_number,
           res => S_FSM_res,
           spare_flag => S_FSM_spare_flag,
           turn_pulse => S_FSM_turn_pulse,
           turn_flag => S_FSM_turn_flag
           
          );
  System_Clk_50MHz <= not System_Clk_50MHz after 10 ns;
  process
    
  begin
    wait until rising_edge(System_Clk_50MHz);
    System_N_Reset <= '0';
    wait until rising_edge(System_Clk_50MHz);
    System_N_Reset <= '1';
    wait until rising_edge(System_Clk_50MHz);
    
    
  end process;  
  
end architecture arc_fsm;

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    and please post the errors

    Plus I also noticed you are asserting reset every 2 clock cycles. you need to wait at the end of the process or it will loop forever.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    error sample

    # ** Error: C:/vhdl/modelsim/state maschine/fsm_tb.vhd(253): (vcom-1136) Unknown identifier "s_m_e_done".# ** Error: C:/vhdl/modelsim/state maschine/fsm_tb.vhd(258): (vcom-1136) Unknown identifier "s_fsm_distance".

    those are signals that were defined at the fsm.vhd and enterd to the components ports
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    s_m_e_done and s_fsm_distance dont exist as signals in the testbench. you need to declare them at the top with all the other signals.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    thanks it's working

    I thought that we only define ports as signal when we make a test bench

    and the we ignore the other logic and signals in the code ...

    So I guess that if signals or constants are been used in a way that implement on other logic we need to define them as well like functions, components ...