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Altera_Forum
Honored Contributor
Honored Contributormodelsim lpm devide error
Hi I am trying to run a simulate in modelsim And I got those errors: # ** Error: C:/vhdl/modelsim/state maschine/Steer_Encoder.vhd(86): Actual (function call "conv_std_logic_vector") for ...
Altera_ForumHonored Contributor
Honored Contributorthanks it's working
I thought that we only define ports as signal when we make a test bench and the we ignore the other logic and signals in the code ... So I guess that if signals or constants are been used in a way that implement on other logic we need to define them as well like functions, components ...
