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Altera_Forum
Honored Contributor
Honored Contributormodelsim lpm devide error
Hi I am trying to run a simulate in modelsim And I got those errors: # ** Error: C:/vhdl/modelsim/state maschine/Steer_Encoder.vhd(86): Actual (function call "conv_std_logic_vector") for ...
Altera_ForumHonored Contributor
Honored Contributorthanks
I added signals and made and called the conv function outside the component and that solved it. but now the compiler gives errors on the components with ports that connecting to signals in the fsm while some ports are external ports other are ports that connect between signals in the general code so the compiler won't recognize them. I can't leave them as open I can't ignore them and I can't insert them to themselves what should I do?
