mixed 3.3V and 1.2V I/O interface

Here is the guidance from the Cyclone III pin connection guidelines:

--- Quote Start ---

Input reference voltage for each I/O bank. If a bank uses a voltage-

referenced I/O standard for input operation, then these pins are used as the

voltage-reference pins for the bank. If voltage reference I/O standards are

not used in the bank, the VREF pins are available as user I/O pins.

If VREF pins are not used, the designer should connect them to either the VCCIO

of the I/O bank in which the pin resides or GND. Decoupling depends on the

design decoupling requirements of the specific board. See Note 5. When VREF

pins are used as I/O, they have higher capacitance than regular I/O pins which will

slow the edge rates and affect I/O timing.

--- Quote End ---

If you are not going to use them as I/O pins, connect them to ground. However, make sure you don't accidentally configure them as I/O in your FPGA design and try to drive a logic high signal out on them.

Jake