Forum Discussion

MAlek2's avatar
MAlek2
Icon for New Contributor rankNew Contributor
7 years ago

MIPI D-PHY transmitter on MAX 10 output buffers

Hello! I'm trying to implement MIPI D-PHY transmitter on MAX 10 Dual supply FPGA.

In Application Note 754 it is written that:

High-speed mode — A differential buffer is used to transmit signals.

Low-power mode — A differential buffer is configured as input mode to act as tri-stated output.

and in high speed mode IO standard is Differential HSTL-18.

In example they used an emulated LVDS, so they could use tristate buffers for each positive and negative LVDS line. But i'm concerned about maximum possible speed with that solution, because i need at least 600 Mbps.

So there are my questions:

  1. Can create a bidir or output with OE LVDS buffer? If yes than how?
  2. Do i really need that buffer? Maybe i can use just LVDS output without OE?
  3. Can i use Bus LVDS IO standard. What maximum speed i can get in this case?

3 Replies

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago
    Hello there , Thank you for the questions , Answer to your questions are below 1. Max 10 use the soft LVDS which wont support the bi-directional flow. you can either configure as TX or RX.To implement the bi-directional mode use the GPIO IP core with differential mode turned ON. 2. Can you please clarify about OE? output enable for transmitter you mean ? I dont know what you mean by " do we really need buffer" If you are using Bidirectional it is require to use OE. 3.For BLVDS as i mentioned you are using the GPIO IP core with differential mode. can you find the date rate of differential IO standrad in below datasheet link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf thank you , Regards, Sree
  • MAlek2's avatar
    MAlek2
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello, thank you for your answer.

    About OE. As written in AN745 to implement MIPI D-PHY with passive resistor network using Intel FPGA one needs to connect two single ended lines through resistors with differential lines. So when Lane in Low Power state, on both of these single ended lines will be a high level signal around 1.2V than will come right to lvds buffer. So i'm afraid that if this lvds buffer does not have anything like output enable signal, that will drive it's lines to high impedance state, it will disturb Low Power state or worse like burn down the internal circuits.

    So my question was, in another words, how can i create D-PHY physics with passive resistor network? What kind of IO standard do i need to assign to my output pins and whether high speed pins should be tristated?

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago
    Hello , Actually if the differential line both the end biased with 1.2V m then the Differential voltage is Logic 0 right ? then the output of the is also logic 0.Please note buffer input impedance is high and output impedance is low.Hence even if you apply 1.2V buffer wont burnt out :) Before answering to your question can i know are you following the AN 745 application notes ?Also are you using the SN65MVVD200A ? Thank you, Regards, Sree