minimum time for IO pin to damage

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is the only difference is the speed

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Yes, mostly. If your application uses only slow logic, the ESD diodes should be fine.

I don't see a particular problem with negative ESD transients, because they are absorbed by the substrate clamp diodes. According to the datasheet, you can expect 10 to 20V spikes for positive and negative standard 1 kV ESD pulses behind the protection device. That's a considerable reduction, but of course, Altera won't guarantee 100% safe operation for the FPGA. At least a two level protection would be needed to keep the maximum ratings strictly. You already said, that there's no room for it.