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Honored Contributor
Honored ContributorMinimal pulse duration for VIC to recognize an interrupt?
Hi I'm using a cyclone III (EP3C40F48I8N) with a Nios II/f . On a custom component I have a tristate slave interface with an "Interrupt Sender". I found out, that a pulse on the irq of 1...
Altera_ForumHonored Contributor
Honored ContributorOh ok. That was what I was missing ;)
It is strange they did it that way, because deferred interrupt handling is necessary in real time OSes... In that case instead of just clearing it, you could disable it in the "Interrupt Enable Register" until you read the data, as you suggest in (1)
