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Altera_Forum's avatar
Altera_Forum
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15 years ago

Minimal pulse duration for VIC to recognize an interrupt?

Hi I'm using a cyclone III (EP3C40F48I8N) with a Nios II/f . On a custom component I have a tristate slave interface with an "Interrupt Sender". I found out, that a pulse on the irq of 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks a lot for all your effort on my problem

Yes, you're right, you can clear the interrupt signal from the LAN9211, that's the first thing I tried - but as the condition for the interrupt is still met (data level >= 1 eth-packet), the LAN9211 will just assert the interrupt again next clock cycle.

There are 2 solutions I see:

1. Disable the interrupt either in the Nios or in the LAN9211.

2. Route the interrupt signal to a PIO component (or similar) which can handle edge-triggered interrupts.

Anyways, thanks for your help, I got some new ideas for my problem now I can try. :)