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Altera_Forum
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16 years ago

Minimal pulse duration for VIC to recognize an interrupt?

Hi I'm using a cyclone III (EP3C40F48I8N) with a Nios II/f . On a custom component I have a tristate slave interface with an "Interrupt Sender". I found out, that a pulse on the irq of 1...
Altera_Forum's avatar
Altera_Forum
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16 years ago

You should keep your IRQ asserted until it is cleared by the software ISR routine. I'm not sure the VIC's behaviour is defined or guaranteed if you clear the IRQ yourself before that.