Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Memory Use Question

Hello Everybody!

I don't know if this is the right section to ask this, if not please do excuse.

I' a student working on the development of a circuit, using VHDL language, and the target it's an Altera Stratix II EP2S60. The circuit needs 4 FIFOs, which were implemented using the function MegaWizard from Quartus, and a RAM (256*8). I'm using the tool Synplify to synthesise the code and the results show that 10% of the M4K memory of the FPGA are used to implement the FIFOs and 2% of the M512 memory are use by the RAM.

Is there any reason why the FIFOs and RAM are implemented on different memories of the FPGA? And why those memory and not the M-RAM?

Thanks for the answers, sorry for my bad English.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    Hi,

    ram size is 256*8 bits = 512 * 4 bits and so cleanly fits 4 M512 blocks.

    all your fifos are too large for M512 and it makes sense to use M4k

    for example the smallest fifo of 512*23 will fit cleanly 23 of M512 blocks or will fit 3 of M4k blocks with 512 bits wasted !!!

    I am a bit disappointed it seems your compiler didn't follow my claim about wasting. It didn't mind that and was more concerned to hold on to the graininess just in case.

    --- Quote End ---

    Hi,

    you mentioned that you use Synplify for synthesis. I assume you mean SynpifyPro.

    If memory usage is an issue in your project, youn can guide SynplifyPro which type of memory should be used for the implemention, by setting a syn_ramstyle attribute in the SDC file.

    Kind regaeds

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    ram size is 256*8 bits = 512 * 4 bits and so cleanly fits 4 M512 blocks.

    all your fifos are too large for M512 and it makes sense to use M4k

    for example the smallest fifo of 512*23 will fit cleanly 23 of M512 blocks or will fit 3 of M4k blocks with 512 bits wasted !!!

    I am a bit disappointed it seems your compiler didn't follow my claim about wasting. It didn't mind that and was more concerned to hold on to the graininess just in case.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi again kaz

    The FIFOs have different sizes:

    512*54

    512*23

    1024*36

    1024*32

    Is this any help? Thanks again for the answer!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    Fifo is treated as any memory and the only reason - I assume - is possibly a difference of size(you haven't stated the fifo size). If each fifo is same size(256*8 bits, as your ram) then the megawizad(or compiler) may have other optimasation plan in mind.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hy kaz

    Thanks for the answer, but is there any reason why the FIFOs are implemented on the M4K and the RAM on the M512? Or the answer is the same, "use the memory graineness in an efficient way with minimum waste"?

    Thanks again!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    In the megawizard you can either choose which memory blocks you want or leave it for the tool(auto). The idea is to use the memory graineness in an efficient way with minimum waste. MRAMs are few and usually used for very large memory needs.