Memory Interface Grouping Assignment

The thing is the synthesizer is stupid, don't try to use Verilog as top level instantiantion, use schematic.

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Hello,

I got pretty the same problem (and I am quite a newbi in Quartus/Verilog).

I generated my NIOS with SOPC Builder.

(I was not able to post the image of the schematic)

I ran the TCL scripts given by SOPC :

-altmemddr_0_phy_ddr_pins.tcl

-altmemddr_0_pin_assignments.tcl

I made clk_n bidirectionnal

I noticed the in my .qsf file this kind of lines

But I still have this kind of error:

Where datas the bidir port I put on my schematic.

Can someone post his assignment file please.

Cordially

trax

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