Honored Contributor
Honored Contributori am having a similar error with ddr3 uniphy.
we have been using xilinx ddr2 in our products. i am exploring an opportunity using ddr3. how do you specify grouping for dq and dqs? can an fae help resolve this? thank you............................................. Error: I/Os have a memory interface specific sub-block, but have no memory interface grouping assignment specified Error: I/O "mem_dq0[0]" has a memory interface specific sub-block, but has no memory interface grouping assignment specified File: ~altera/mcu/rtl/mcu_altdqdqs.sv Line: 1368 Info: stratixiv_io_config atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|pad_gen[0].config_1" Info: stratixiv_output_phase_alignment atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].data_alignment" Info: stratixiv_output_phase_alignment atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].oe_alignment" Info: stratixiv_output_phase_alignment atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].oct_alignment" Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_oct" Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_oe" Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_hi" Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_lo"
