Memory Interface Cyclone 3

ZBT just reduces the read/write turnaround, not the pipeline latency.

As said, there is a natural compromise between latency and throughput. You must decide which one is more important for you. For smaller latency you may want flow-through SSRAM. This would give you one cycle read latency.

If you really want just half cycle latency, then you would need to use async SRAM, or either use a PLL to double (or even just delay) the external clock. Either way, you probably would need to reduce the clock frequency.