Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMemory Interface Cyclone 3
I am wondering what the fastest memory interface would be for the cyclone three. Q1. What is the fastest RAM chip supported by altera IP or that works with cyclone 3? Q2. What is the fastest ...
Altera_ForumHonored Contributor
Honored ContributorZBT just reduces the read/write turnaround, not the pipeline latency.
As said, there is a natural compromise between latency and throughput. You must decide which one is more important for you. For smaller latency you may want flow-through SSRAM. This would give you one cycle read latency. If you really want just half cycle latency, then you would need to use async SRAM, or either use a PLL to double (or even just delay) the external clock. Either way, you probably would need to reduce the clock frequency.
