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Altera_Forum's avatar
Altera_Forum
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10 years ago

Measuring delay from a PLL output to an FPGA pad

Hi

I have a PLL with two outputs: c0 & c1.

The clock c0 feeds logic.

The clock c1 goes to an external FPGA pin & feeds an external device.

How can I measure delay between that PLL output (c1) and the FPGA pad using TimeQuest?

I tried using report_timing commands as follow, but I got no path:

report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -setup

report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -hold

report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -recovery

report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -removal

Probably the report_timing command reports paths which are clocked by a clock, and since there is no register after that PLL output no path is found.

Any idea?

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    yes, if the clock is not connected to any register, it would be consider normal routing.

  • Altera_Forum's avatar
    Altera_Forum
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    report_timing requires a constraint. If you don't have a set_output_delay constraint on the output, it won't analyze anything. But TQ can analyze "clock as data", which is what you want.

    You could also try report_path, which doesn't require a constraint.

    I'm guessing you have a source-synchronous output, i.e. you're sending data out and want it aligned with the clock. It sounds like you're trying to do this by hand, e.g. find out how long it takes the clock to get out and then compare that to data. It's a lot more complicated than this though, as there are multiple timing models that need to be analyzed, there is on-die variation within the model that needs to be accounted, etc. If it is source-synchronous, I would recommend looking at:

    http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest