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Honored Contributor
10 years agoMeasuring delay from a PLL output to an FPGA pad
Hi
I have a PLL with two outputs: c0 & c1. The clock c0 feeds logic. The clock c1 goes to an external FPGA pin & feeds an external device. How can I measure delay between that PLL output (c1) and the FPGA pad using TimeQuest? I tried using report_timing commands as follow, but I got no path: report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -setup report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -hold report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -recovery report_timing -from {u_pll_125|altpll_component|auto_generated|clk[1]} -removal Probably the report_timing command reports paths which are clocked by a clock, and since there is no register after that PLL output no path is found. Any idea? Thanks