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Altera_Forum
Honored Contributor
11 years agoMeasuring delay from a PLL output to an FPGA pad
Hi I have a PLL with two outputs: c0 & c1. The clock c0 feeds logic. The clock c1 goes to an external FPGA pin & feeds an external device. How can I measure delay between that PLL output ...
Altera_Forum
Honored Contributor
11 years agoyes, if the clock is not connected to any register, it would be consider normal routing.