Measuring delay from a PLL output to an FPGA pad

report_timing requires a constraint. If you don't have a set_output_delay constraint on the output, it won't analyze anything. But TQ can analyze "clock as data", which is what you want.

You could also try report_path, which doesn't require a constraint.

I'm guessing you have a source-synchronous output, i.e. you're sending data out and want it aligned with the clock. It sounds like you're trying to do this by hand, e.g. find out how long it takes the clock to get out and then compare that to data. It's a lot more complicated than this though, as there are multiple timing models that need to be analyzed, there is on-die variation within the model that needs to be accounted, etc. If it is source-synchronous, I would recommend looking at:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest