Me and my simple questions: Can I do this in FPGA?

Your friend doesnt know much. Altera provides floating point cores to do floating point arithmatic. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altfp_mfug.pdf

While you wouldnt be using much VHDL, you are designing a circuit. The VHDL would just glue the cores together.

But floating point in FPGA does have it's issues - it has high resource usage and high latency. If you have a constant data stream then the FPGA can process far more than a processor could handle (it can do it in real time - you basically build a custom co-processor). But if it's just a few calculations then it's probably easier to let an arm do the work.

So the answer is "Yes it can do it". But you will need to think seriously about how to implement it.

Tricky right. You can

But your equation can be more optimized to parallel computation) and should be rewritten as you compute power. it depends how data stream come

You have to use floating point cause you need exponent and logarithm or you can build your own for integer data type or fixedpoint

y**x = 2**(x*log2 y) if y > 0.

avoid division and use rational approach 1/x = x**(-1) = 2**(-log2 x) , x>0.

You can rewrite your equation fully in 2**x and log2 x function.

if you need to compute sum the problem of accuracy still exists. you have to remember if you will add unsorted floating-point. Does it take place in FPGA?

When the proper units are chosen, very few caculations in the physical world cannot be done with 64 bit (or higher) integers. DSPs were for a long time strictly integer many techniques developed then are apply to FPGAs. Look into these techniques and take another look at how your problem might be solved with them.

I don't recommend using the floating point FPGA blocks that are available. They waste FPGA resources and aren't needed with some careful analysis of the problem. The same goes for floating point in OpenCL and Vivado HLS.

Oh. If Galfonz recommend using dsp I suggest you find docs about transformation based on fft for arithmetic operation with big integers

It is not on surface. Even googling web cannot provide fast answer

Thanks so much guys, I'll carefully study all your answers. My professor says I don't need to use Floating point unit for this, he says by designing a simple Adder-Multiplier-Accumulator would be enough (maybe is what Galfonz is mentioning). I will implement this on my FPGA but what i'm intending is to simulate a Chip which can perform this equation.

I have another question, this Floating Operation Module on the FPGA, Can it serves to several PE at the same time? Or it's a single module that will serve one PE one at a time? I ask this because I may need to do this equation in several PE at the same moment in paralell.

It has a single input and a single output.

But if the data rate is half the clock rate, you can mux the input between two sources.

--- Quote Start ---

Thanks so much guys, I'll carefully study all your answers. My professor says I don't need to use Floating point unit for this, he says by designing a simple Adder-Multiplier-Accumulator would be enough (maybe is what Galfonz is mentioning). I will implement this on my FPGA but what i'm intending is to simulate a Chip which can perform this equation.

--- Quote End ---

Hi, Before to build a MAC unit you can found ready to use or make from scratch if this is your course goal, you need do some analysis of math underneath the equation you posted, so from where are coming Xi m Ci Cj and how long is summation and where data is stored? If you need retrieve from main memory then maybe really the DE1 Arm core can do better.

MAC unit is the base of DSP processing, better knowledge of data handling is a start point to evaluate faster and precise solution.

--- Quote Start ---

I have another question, this Floating Operation Module on the FPGA, Can it serves to several PE at the same time? Or it's a single module that will serve one PE one at a time? I ask this because I may need to do this equation in several PE at the same moment in paralell.

--- Quote End ---

To answer to this question is again necessary to know how indexes and parameter are handled, you can build a block and replicate on FPGA to compute more than one result as a SIMD or MIMD architecture but this need data get not overwritten from result, so:

where are to be stored uij results, from where are taken Xi Cj Ck m C, are same on input and output vector/matrix?

Hey rromano001, I have been doing an analysis. All what I say is from my ignorance, so you guys are free to correct me, First I must say that I won't be able to make this using the nice resources of my DE1 because my intention is to design a system that can handle not 2 or 3 PE but hundreds PE communicating each other in a torus network. Each of them have to be able to perform Adding, Subtraction, Multiply and Divide to perform the purposed Equation.

Regarding Floating Processing Unit I think is not necessary to make this kind of unit, Since I don't require so exact accuracy. Instead, I will use a very exact Fixed point method, making use of a group of registers to be filled with BCD numbers divided like this

88 . 88888888 (base-10) = 1000 1000 . 1000 1000 1000 1000 1000 1000 1000 1000 (Binary)

I'm pretty sure this would be enough, I did a couple of calculations with examples values and they never overpasses these limits and when they do, it doesn't matter for my purpose.

Input data can come directly in BCD directly or be converted from base-10, it doesn't matter.

Then I will construct the modules for each of operations, Adding, Subtraction, Multiply and Divide for separated. Something that I've found is that VHDL is a REALLY low language, I suspect I cannot directly operate two decimal numbers, but like in Assembler, I have to convert them to BCD and make operations of arithmetic adding, complements (for subtraction), carry, etc, in order to be able to Add decimals numbers. am I right??

Being honest, my professor seems not to have a single IDEA of what I'm doing, he is more of high level language, and he seems to think arithmetic operations is so simple as to start code and call it a day. :(

Why do you want to use bcd? That makes things very complicated and use a lot of resources. Why not just work in binary like every other language? You can easily do arithmatic in vhdl with the IEEE.numeric_std library

A <= b + (c*d);