Me and my simple questions: Can I do this in FPGA?

--Programando SUMADOR como un Registro--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

use ieee.fixed_pkg.all;

entity SUMADOR is

port

(

-- Input ports

numero1 : in ufixed (2 downto -7);

numero2 : in ufixed (2 downto -7);

resultado : out ufixed (2 downto -8);

clk : in std_logic

);

end SUMADOR;

architecture arc_sum of SUMADOR is

begin

process (clk) begin

if (clk'event and clk='1') then -- when clock rise up--

resultado <= numero1 + numero2;

end if;

end process;

end arc_sum;