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Altera_Forum
Honored Contributor
Honored ContributorMe and my simple questions: Can I do this in FPGA?
Hi dear Altera friends. Sorry for the simple questions, i'm a beginner. My FPGA is DE1-SoC University, i'm learning how to use it. My question today is the following one: Until now, with t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Tricky thanks for fast response. I edited the downloaded files to not use IEEE_PROPOSED but just leave IEEE. Quartus Prime compiles without error, but Modelsim give several lines of this error What do you recommend to do? Also, I'd like to ask: If Quartus Prime is compiling good, it means the project is doing good? How can I see the result of the addition I'm doing?? is it trough modelsim? --- Quote End --- try this simple book http://freerangefactory.org/books_tuts.html If quartus compile good is not sign things work, logic can be wrong or timing or other infinite thing more subtle than from a c language perspective. Hardware generated image can fail
