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DDina's avatar
DDina
Icon for New Contributor rankNew Contributor
7 years ago

May I not supply voltage to VCCIO during power up and configuration?

Hi.

Internal weak pull-up resistors interfere with my scheme. As far as I know the pull-up resistors cannot be disconnected during power up and configuration. May I not supply voltage to VCCIO?

​​​​​​​How long may I not supply voltage to VCCIO? I configure FPGA using my computer.

I use Cyclone V - 5CEFA2F23C8.

4 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    We have to supply VCCIO. If VCCIO is not powered, configuration will fail. The POR circuitry keeps the Cyclone V device in the reset state until the power supply outputs are within the recommended operating range.

    1. The output buffers are tri-stated during system power up or power down,All user I/O pins are tri-stated during configuration.
    2. The POR circuitry monitors the voltage level of the power supplies and keeps the I/O pins tri-stated until the device is in user mode.

    Reference page 142 & 318.

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

    Let me know if you need any further assistance.

    Best Regards,

    Anand

    • AnandRaj_S_Intel's avatar
      AnandRaj_S_Intel
      Icon for Regular Contributor rankRegular Contributor
      7 years ago

      Hi,

      Yes, All I/Os pins are tied to an internal weak pull-up during Power Up and Reset.

      Coming back to the question

      1. May I not supply voltage to VCCIO during power up and configuration?.Yes, VCCIO is not required for power up and configuration.

      2.How long may I not supply voltage to VCCIO?

      VCCIO is not monitored by POR so it can be as long as you like.

      We can power up VCCIO for IO banks individually after configuration based on our design requirements.

      Let me know if you need any further assistance.

      Best Regards,

      Anand