Maximum output pin current for 3.0 V LVTTL with 2.5 V supply

Hi Jacob,

you find your answer in the device data sheet: https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf#page=17.

Cheers,

fade

That table seems to be for the applicable current to meet I/O standard specification, not the maximum current the pin can supply.

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"Table 20: Single-Ended I/O Standards Speci€cations for MAX 10 Devices"

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The question title " 3.0 V LVTTL with 2.5 V supply" sounds still confusing. 3.0V LVTTL specifications are for 3V rather than 2.5 supply. You won't find a specification for output current with wrong supply voltage. It can be derived if you understand the relation of current strength settings and supply voltage, but that's beyond supported specifications.

Still not sure what you mean with "maximum output pin current"? Under which conditions? Which current strength settings?

In any case you should consider that with higher current strength, the actual output current may be above maximum rating of +/- 25 mA so that the output driver might be damaged.

For a complete specification of output characteristics review MAX10 Ibis files. https://www.altera.com/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html

Going back to this, I can see how my question was confusing.

What I would like to do, is draw the highest possible current I can from a number of paralleled output pins, to drive for example a MOSFET gate as quickly as possible.

This is not for continuous switching.

I will simulate with the IBIS file.

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What I would like to do, is draw the highest possible current I can from a number of paralleled output pins, to drive for example a MOSFET gate as quickly as possible.

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O.K., I don't expect that setting LVTTL30 with 2.5V supply brings any advantage in this situation. The basic point to understand is that the different drive strength configurations share a limited number of output transistors for each pin driver that can be combined to achieve the intended output current, impedance, whatsoever. There are a few cases where faking a wrong VCCIO gives you additional choices (with the risk of possibly exceeding maximum ratings), but I don't think in this case.

In any case, maximum current ratings per pin and IO bank should be observed. Unfortunately there are no clear dynamic ratings (similar to a transistor SOA diagram) to determine permissible capacitive load. But beyond maximum ratings, you should consider that driving capacitive loads brings up ground bounce issues and should be avoided if possible.

Yes, I will have to use the rating that are given.

Good point about GB, but it's not a large capacitance, and the trace inductance will be kept low. It could for example be 110 pF gate capacitance such as for Microchip's TC6320.