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What I would like to do, is draw the highest possible current I can from a number of paralleled output pins, to drive for example a MOSFET gate as quickly as possible.
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O.K., I don't expect that setting LVTTL30 with 2.5V supply brings any advantage in this situation. The basic point to understand is that the different drive strength configurations share a limited number of output transistors for each pin driver that can be combined to achieve the intended output current, impedance, whatsoever. There are a few cases where faking a wrong VCCIO gives you additional choices (with the risk of possibly exceeding maximum ratings), but I don't think in this case.
In any case, maximum current ratings per pin and IO bank should be observed. Unfortunately there are no clear dynamic ratings (similar to a transistor SOA diagram) to determine permissible capacitive load. But beyond maximum ratings, you should consider that driving capacitive loads brings up ground bounce issues and should be avoided if possible.
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