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Altera_Forum
Honored Contributor
Honored Contributormaximum clock speed for cyclone iv
hello everyone, we have bought a de0-nano board for our project. it has an 50 mhz clock. what i want to ask, what is the maximum clock rate to apply cyclone iv externally? or, more clear, can we...
Altera_ForumHonored Contributor
Honored ContributorLook at Table 1–25. PLL Specifications for Cyclone IV Devices (p470)
http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf The maximum for a PLL input is 472MHz. If you read on further, you will see that 433MHz is too fast for a GPIO pin. Keep in mind that you could divide the external clock and then use a PLL internal to the FPGA to increase the clock frequency. Cheers, Dave
