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KrishnamRaju's avatar
KrishnamRaju
Icon for New Contributor rankNew Contributor
2 years ago
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MAXII to MAX5 CPLD foot print compatability

Dear Team We are chaning MAX CPLD II EPM2210F256C5N with MAX V CPLD 5M2210ZF256I5N . 1. Are both CLPDs foot print compatiable? 2. In my old design for MAXII VCCINT 3.3V is there and Now I am chang...
Programmable Logic Device
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    It's all described in device handbook and datasheet.

    GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.

    "Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."

    Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.

    Regards
    Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi Krishnam,
I'd rely on MAX V hot socketing specifications in this regard:

■ The device can be driven before and during power up or power down without
damaging the device.
■ I/O pins remain tri-stated during power up. The device does not drive out before
or during power up, thereby affecting other operating buses.
■ Signal pins do not drive the VCCIO or VCCINT power supplies. External input signals
to the device I/O pins do not power the device VCCIO or VCCINT power supplies
using internal paths. This is true if the VCCINT and VCCIO power supplies are held at
GND.

Entry into user mode is gated by whether all the VCCIO banks are powered with
sufficient operating voltage. If VCCINT and VCCIO are powered simultaneously, the
device enters user mode within the tCONFIG specifications. If VCCIO is powered more
than tCONFIG after VCCINT, the device does not enter user mode until 2 µs after all VCCIO
banks are powered.

Not sure where you see weird behaviour. According to device handbook, the described operation conditions are acceptable.

KrishnamRaju's avatar
KrishnamRaju
Icon for New Contributor rankNew Contributor
2 years ago

Dear Frank

Thank you for your valuable reply.

We are giving only I/O banks power and not providing core power. What is the state of I/Os in this case?

Is It ok to keep MAX V CPLD in this state?

We are suspecting some assembly issue of this device and want to keep this device out of picture.

Thank you