Forum Discussion
New ContributorMAXII to MAX5 CPLD foot print compatability
Hi,
It's all described in device handbook and datasheet.GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.
"Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."
Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.
Regards
Frank
Super ContributorHi,
It's all described in device handbook and datasheet.
GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.
"Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."
Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.
Regards
Frank
New ContributorDear Frank
We want to Keep MAX-V CPLD without giving Core power and one Bank I/O power(Bank 3 1V8) (As we are not using this). But due to our design limitation we are giving power to other 3 I/O banks. Is it ok?
Some of the I/os(Not powered) are connected to the Processor . In this condition our power circuit is beahaving weirdly.
Is it ok to keep CPLD in this condition or better to remove this IC from the board?
With Regards
Krishnam Raju M
