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KrishnamRaju's avatar
KrishnamRaju
Icon for New Contributor rankNew Contributor
2 years ago
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MAXII to MAX5 CPLD foot print compatability

Dear Team We are chaning MAX CPLD II EPM2210F256C5N with MAX V CPLD 5M2210ZF256I5N . 1. Are both CLPDs foot print compatiable? 2. In my old design for MAXII VCCINT 3.3V is there and Now I am chang...
Programmable Logic Device
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    It's all described in device handbook and datasheet.

    GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.

    "Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."

    Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.

    Regards
    Frank

NazrulNaim_Intel's avatar
NazrulNaim_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Best regards,

Nazrul Naim


  • KrishnamRaju's avatar
    KrishnamRaju
    Icon for New Contributor rankNew Contributor
    2 years ago

    Dear Naim

    Please help us on below poits,

    1. Before programming the CPLD MAX V, What are the default states of all I/Os.

    Initiall after power up all I/Os(Before programming the CPLD) are driving some logic to processor beacuse of which I am facing some issue.

    2. I want to keep all un used pins as input with high impoedence after programming the CPLD. How to make this setting in Quartus tool.

    With Regards

    Krishnam Raju M