Forum Discussion
New ContributorMAXII to MAX5 CPLD foot print compatability
Hi,
It's all described in device handbook and datasheet.GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.
"Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."
Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.
Regards
Frank
Regular ContributorHi Krishnam Raju M,
Sorry for the delay. For your information since MAX II and MAX V are both different device which you have stated T6 pin which is ground in MAX V is I/O in MAX II. Thats why the pin assignment is different from each other.
For more information you can access these links for the device handbook for MAX II and MAX V
Link MAX II: https://cdrdv2.intel.com/v1/dl/getContent/655094?explicitVersion=true&fileName=max2_mii5v1.pdf
Link MAX V: https://cdrdv2.intel.com/v1/dl/getContent/654928?explicitVersion=true&fileName=max5_handbook.pdf
Hope that helps.
Best regards,
Nazrul Naim
New ContributorDear Naim
Thank you.
1. I had already mounted MAX-V in place of MAX-II.
2. I found only T6 as the difference which was used as GPIO in my design. This GPIO is not crucial for my design. Can I gohead with testing?
Will it create any problem?
With Regards
Krishnam Raju M
