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KrishnamRaju's avatar
KrishnamRaju
Icon for New Contributor rankNew Contributor
2 years ago
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MAXII to MAX5 CPLD foot print compatability

Dear Team We are chaning MAX CPLD II EPM2210F256C5N with MAX V CPLD 5M2210ZF256I5N . 1. Are both CLPDs foot print compatiable? 2. In my old design for MAXII VCCINT 3.3V is there and Now I am chang...
Programmable Logic Device
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    It's all described in device handbook and datasheet.

    GPIO have weak pull-up resistors to respective VCCIO until user mode becomes active. State of unused pins can be globally selected in Quartus device and pin options.

    "Reserves all unused pins on the target device in one of 5 states: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up."

    Personally, I won't choose high-Z without pull-up if there are any unconnected GPIO pins because floating inputs can involve additional device current consumption.

    Regards
    Frank

NazrulNaim_Intel's avatar
NazrulNaim_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,

Sorry for the delay. As user 'FvM' have replied. The reply can be accepted which is the devices are pin compatibility and need to check the signal assignments by importing the MAX II pin assignments to MAX V design. Do let me know if I can assist you further.

Best regards,

Nazrul Naim

  • KrishnamRaju's avatar
    KrishnamRaju
    Icon for New Contributor rankNew Contributor
    2 years ago

    Dear Naim

    I found a T6 pin which is ground in MAX V is I/O in MAX II.

    Can you please look at this and the reason for this difference.

    With Regards

    Krishnam Raju M