Honored Contributor
Honored ContributorOkay, i'm still stuck on this issue. Here's what i have accomplished today:
1) I added states to my FSM that allow me to read out the 256 first DWORDs from the programmed flash. 2) I programmed the flash via USB-Blaster/MAXII with a known good user configuration .pof file 3) I then power-cycled the Cyclone IV GX Dev Kit and read out the first 256 flash words - data ended up in SignalTapII trace. 4) I then compared the Signaltap data with the data in the RBF file. 4) It turns out that the flash contained two initial 0001, 033c words before 16xFFFFs and the rest of the RBF data. So I, thinking that the 0001, 033c were magic numbers that the PFL put into flash when programming the data, modified by PC code to program the 0001, 033c before programming the RBF data. Unfortunately, the FPGA will not configured from the user configuration in flash. Could the initial 0001, 033c be a checksum or perhaps some length field? I will do more analysis of this tomorrow. It is quite frustrating that Altera has provided a PFL via FPP and even a Remote Update block that is supposed to facilitate FPGA upgrade/programming via FPGA but fails to actually document what needs to be programmed into flash. This is way too much trial and error for using supplied IP and tools...
