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Altera_Forum's avatar
Altera_Forum
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9 years ago

MAX10M25SC which pins needed for 64io use?

Hello all. I am new to FPGA, and will be using the basic elements of a current processor Veriloh that have been shared online. The goal is to create a 64io device similar to the current processors 32io design, the code they have made public already has it available to use 64io to replicate the true 64io processor. I am working on the Eagle library and a new board to test with, similar to the BE Micro Max 10. That board has analog and a dual power, dual image, I will not use A or D and am using SC version. I have not yet found a reference schematic for the SC version Max10, so I wanted to find out if I can just remove the connections that are currently on analog sections. Likewise, there are lots of different pins with different descriptions. I am looking for 64 basic IO to behave like a normal processor would. Any guidelines on which pins would be best for the 64io? For unused io, can they float or does every unused pin need to be pulled down?

I am sure to have more question as the board progressed, but at least this gets the basics under way. I tried opening the brd file included in the eval board docs, but am getting an error on load, but at least I have the schematics for the eval board for dual power, analog. I am trying to assess what is the bare minimum connection required.

Thanks.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Look through the Recommended Operating Conditions section, and particularly table 6 on page 4 of the "max 10 deveice datasheet (https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf)". This very clearly explains what rails should be powered and how.

    Also look through the "pin connection guidelines (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/max-10/pcg-01018.pdf)". This covers all the pins on the device and what you need/should do with each.

    As for your I/O that will "behave like a normal processor" - any of the pins whose function is identified as "IO" in the device pinout can be made to behave as a GPIO pin might on a processor.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Thanks for that info, very helpful. I am also interested to see if FTDI FT2232H with JTAG is an option to load the MAX10. I am not really clear yet on how this works until I get the eval board in next week, and am trying to understand the process.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Are you considering developing your own loader based on a FT2232H device? "I am new to FPGA" - try walking before you run. Use altera's usb-blaster (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_usb_blstr_ii_cable.pdf) for development. You can 'load' your MAX 10 using that. Depending on the MAX 10 kit you've ordered a programming solution (USB-Blaster on board) may come as part of the kit. Forgive me if I've misunderstood but I don't think developing your own programmer/loader is where you should be focusing your efforts.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Alex Thanks for the info. I am mostly done with a complete new board design using the MAX10M25SC that includes a JTAG connection, so I can use one of the variants of loaders for immediate use. However I want to include an embedded loader to test as this board is a predecessor to a system, and it would be best to include a USB port now on the first PCB order to get it sorted out, as in the real world my system must have USB for loading for the consumer to use, not a USB blaster. That is why I have looked at FTDI's device which includes JTAG functionality. However, if it were known already that the device does or does not work, that info would be nice to know in advance.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I can't advise as to whether it will work or not. The device can be used as a JTAG host via USB. So, it certainly looks to be the part. However, you will have to consider what drivers you are going to use to control your on-board JTAG host and programming of the FPGA. You won't be able to rely on any Altera software/drivers for that. It's designed to support a USB-Blaster and not a custom solution such as you're proposing.

    Cheers,

    Alex