TWell6
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New ContributorMAX10 Timing Constraints for a Clock Enable fanout?
I'm working on a project for a MAX10 FPGA, using a clock enable, ClkEnBuffer, which reduces the clock speed by 4. I've had a look at a Timing Analyzer example (https://www.intel.com/content/www/us/e...
Your hold multicycle value should be one less than your setup multicycle, so it should be 3 instead of 1. The example you link to has enable every other cycle which is why 2 and 1 are used there. You need to use 4 and 3 for your enable every 4 cycles. Try that and report back.
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