Forum Discussion
Altera_Forum
Honored Contributor
8 years agoNew to the FPGA world, but been working with Altera PLD for many years.
The issue was the configuration pins, even though you can disable the configuration pins in the project settings, the config pins must still have pull ups on the ConfigSel, nConfig, and nStatus lines or intermittent behavior is seen on power up. Future note, if dual purpose is used on these pin, not sure all cases would actually work properly.