Forum Discussion

Rodo's avatar
Rodo
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

MAX10, Nios 2: Intel FPGA Avalon I2C (Master) example ?

Is there a complete example (with buffer connections) of using this IP core in a nios system?

I added the IP core to nios and generated the tri-state buffers with the GPIO Lite core but now I'm lost. The Intel Embedded Peripherals IP User Guide says that I can instantiate these buffers in my top design. I called my bufferes: i2c_scl_buffer and i2c_sda_buffer. I clicked "yes" after making them to add the files to my project. Did that instantiate them already or do I have to do it and if so how? A full example would be nice. All help I get seems to tell me to use opencoreip ... I'm trying to use the intel i2c core and the intel tri-state buffers. Thanks

10 Replies

    • Rodo's avatar
      Rodo
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      @sheng

      The first and last links are broken. I checked rocketboards and I found nothing. I know the design store has none because that was the first place I looked.

      I just tried premiersupport.intel.com and I got the following message:

      You don't have Access to IPS.
      Please contact the FAE to get access.

      No link to how to find the local FAE was given. I'm in Southern California (Los Angeles county).

      Is everything with intel this frustrating?

      • ShengN_altera's avatar
        ShengN_altera
        Icon for Super Contributor rankSuper Contributor
        4 years ago

        @Rodo

        I'll get to internal expert on this to see whether there is any example available or any suggestion. Will come back to you if any feedback from them.

  • Rodo's avatar
    Rodo
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    @ShengN_Intel:

    I appreciate what you're doing. Intel reply to my inquiry is below. I said I was "playing" with the kit because I don't have an active project for a MAX10. I'm a self-employed EE consultant. I'm doing this because a customer asked me about using an FPGA for his design. Right now his design does not need an FPGA but I wanted to be ready if the design grows some more.

    I'm getting the idea that the "Intel FPGA Avalon I2C (Master)" IP core doesn't really work.

    Here is the reply from support:

    ------------------------------------------------------------------------------------------------------------------------------------------

    Thank you for contacting Developer Zone support.

    We hope you are doing great.

    We are sorry for the inconvenience. Unfortunately, your query reached Developer Zone support. The support for this product is provided only in the public forum by the developer community and our tech experts. You can post your query in the below-mentioned link to get further assistance.

    Community Forum Link: https://community.intel.com/t5/Programmable-Devices/bd-p/programmable-devices

    We wish to get your query addressed sooner by our community experts. Proceeding further, we are closing this ticket.

    --------------------------------------------------------------------------------------------------------------------------------------------

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi Rodo,

    There are no examples available for this. What i can suggest is you have to make port interconnection between buffer module added and top module. Make sure the .qip file added as well. Below attached a simple example to show you the port interconnection between sub-module and top module.

    Thanks,

    Best regards,
    Sheng

    • Rodo's avatar
      Rodo
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Thanks but I got that part from a reply (comment) to my post at stackoverflow. How to instantiate in verilog : https://stackoverflow.com/questions/20066850/verilog-how-to-instantiate-a-module . It would be more helpful if the example you provided used the actual names for the intel i2c ip core. Curious, why you guys can offer this example but not a complete one? Are there any licensing issues? Thanks anyway.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi Rodo,

    I created another sample file attached below which involves interconnection between Avalon I2C (Master) module with example buffer module (verilog) from manual. Hopefully, you have a better understandings on that.

    • ShengN_altera's avatar
      ShengN_altera
      Icon for Super Contributor rankSuper Contributor
      3 years ago

      Hi Rodo,

      Any further update on this?

      Best regards,
      Sheng

      p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

      • Rodo's avatar
        Rodo
        Icon for Occasional Contributor rankOccasional Contributor
        3 years ago

        @ShengN_Intel:

        I don't know. I tried to add some code but I think I run out of (internal) RAM so I'm switching to external RAM but I'm having problems getting it to work. I'll go back to I2C when I get the external RAM to work. I suppose you can close this. I'll post a new question if I need to. Thanks.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi Rodo,


    If so I'll close pending this thread then.

    I'll now transition this thread to community support.

    If you have a new question, feel free to open a new thread to get the support from Intel experts.


    Thank you.


    Best regards,

    Sheng

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.