Forum Discussion

patrick03's avatar
patrick03
Icon for New Contributor rankNew Contributor
8 hours ago

MAX10 FPGA IOs not entering Tri-state (Hi-Z)

Hello Team,

I am using 10M16 FPGA and observed that the IOs are not getting tri-stated/ Hi-Z state after:

  1. The Reset is released through a switch / press button on "DEV_CLRN" pin, considering there is no .sof/ .pof code flashed.

Hardware Configuration: 

  1. "DEV_OE" pin is Grounded with 10K resistor.

Reference: Intel® MAX® 10 Device Handbook - Combined 

Pin NamePin FunctionsPin DescriptionConnection Guidelines 
DEV_OEInput, I/O This is a dual-purpose pin. Optional pin that allows you to
override all tristates on the device.
When this pin is driven low, all I/O pins are tristated. When
this pin is driven high, all I/O pins behave as programmed.
You can enable this pin by turning on the Enable device
wide output enable (DEV_OE) option in the Quartus Prime
software.		Altera recommends you to tie the DEV_OE pin to GND when
the Enable device-wide output enable (DEV_OE) option
is disabled and not used as a user I/O pin. You can also tie
the DEV_OE pin to VCCIO or leave the DEV_OE pin
unconnected provided that the Enable device-wide output
enable (DEV_OE) option is disabled and not used as a user
I/O pin. When you leave the DEV_OE pin unconnected, Altera
recommends you to set the DEV_OE pin to input tristate with
a weak pull-up.
Configuration

1 Reply

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 hour ago

    Hi Patrick,

    I believe this is a misunderstanding. DEV_OE pin is only functional in user mode (with valid configuration loaded) when enabled in device and  pin options. Default IO pin state is three-state with weak pull-up, that's what you'll see before loading .sof or configuration from non-volatile memory.

    Regards
    Frank