MAX10 for 5V LVTTL interface

Hello,

Let me work through each aspect of your scenario and flag the risks and gaps I can confirm from the documentation.

What the documentation confirm works in your favor:

MAX 10 devices support hot socketing (hot plug-in/hot swap) and power sequencing without the use of external devices: MAX 10 FPGA Design Guidelines

So during power-up, your 5V bus driving into the MAX 10 I/O pins is handled by the hot-socketing circuitry.

Before or during power up or power down, you can drive signals into I/O pins, dedicated input pins, and dedicated clock pins without damaging the MAX 10 devices. Drive Intel MAX 10 Devices Before Power Up

The hot-socketing feature tri-states the output buffer during the power-up (VCCIO or VCC power supplies) or power-down event. The hot-socketing circuitry generates an internal HOTSCKT signal when VCCIO or VCC is below the threshold voltage during power up or power down. The HOTSCKT signal cuts off the output buffer to ensure that no DC current leaks through the pin. Hot-Socketing Feature Implementation

The design of the I/O buffers and hot-socketing circuitry ensures that the MAX 10 device family is immune to latch up during hot-socketing. I/O Pins Remain Tri-stated During Power up

The critical gap - clamping diodes are NOT active until fully configured:

This is the most important risk in your scenario that you need to carefully consider. The internal clamping diodes in the MAX 10 devices are composed of circuits that are enabled only in a fully configured device. So, unless the device is completely powered up and configured, the internal clamping diodes do not exist. If while these devices are unconfigured, you are driving signals that require clamping diodes into them, in order to limit overshoot or undershoot, use external clamping diodes to avoid damaging the device. Are the internal clamping diodes on Intel® MAX® 10 or Intel® Cyclone® 10 LP devices active at all times?

This is a significant gap in your plan: during POR and configuration, the hot-socketing circuitry protects against DC current leakage and latch-up, but the PCI clamp diodes are simply not present yet. The hot-socketing circuitry and the PCI clamp diodes are two separate protection mechanisms, and only one of them is active pre-configuration.

I/O bank output behavior:

A single I/O bank supports output signals that are driving at the same voltage as the VCCIO. An I/O bank can simultaneously support any number of input signals with different I/O standards. MAX 10 FPGA Design Guidelines So your bidirectional configuration is architecturally valid for the input direction, but the output side will drive at 3.3V VCCIO levels.

OCT RS mixing note:

OCT RS are supported in the same I/O bank for different I/O standards if they use the same VCCIO supply voltage. MAX 10 FPGA Design Guidelines Keep this in mind if you're using on-chip termination anywhere in the same bank.

Summary of risks you may not have fully covered:

Pre-configuration window: During POR and configuration, the PCI clamp diodes are inactive. If your 5V bus is actively driving during this window, the pad sees the full 5V swing with no clamping. The hot-socketing circuitry will tri-state the outputs and prevent latch-up, but it does not clamp the input voltage. You need external clamping diodes on any pin that will see >VCCIO+0.5V during the pre-configuration window, as the documentation explicitly recommends.

No Altera-documented 5V use case: You are correct that Altera does not document a 5V-tolerant use case for MAX 10. The PCI clamp diode feature is documented for 3.3V PCI signaling environments, not 5V LVTTL. The absolute maximum ratings and the 4.12V/11-year reliability figure you reference are from the datasheet, but operating continuously at or near absolute maximum is inherently outside the characterized operating envelope.

CONF_DONE pin specifically excluded from hot-socketing: The hot-socketing circuit does not include CONF_DONE and nSTATUS pins to ensure that these pins are able to operate during configuration. Thus, it is an expected behavior for these pins to drive out during power-up and power-down sequences. Hot-Socketing Feature Implementation If any of these configuration pins are on your 5V bus, they have no hot-socketing protection at all.

I hope these information helps.